1. Field of the Invention
The present invention relates to a switching regulator using a PLL circuit, and more particularly to a switching regulator which controls power loss during anomalous operation.
2. Description of the Related Art
A switching regulator is used in many electronic devices. A switching regulator generally converts an input voltage to a predetermined voltage that is supplied to circuits in the device.
There is currently demand to reduce power loss in such switching regulators in conjunction with the need to reduce power consumption. Japanese Laid-Open Patent Publication No. 2004-201373 discloses a method for reducing power loss in a switching regulator. The art disclosed in Japanese Laid-Open Patent Publication No. 2004-201373 reduces power loss by providing a timing by which to reduce the current and voltage supplied to a transistor, and switching the current and voltage using this timing.
Although the switching regulator of Japanese Laid-Open Patent Publication No. 2004-201373 is not described in detail, a PLL (Phase Locked Loop) circuit is considered for use as a circuit for controlling switching elements such as transistors.
FIG. 1 is a diagram showing a configuration of a conventional switching regulator using a PLL circuit. A conventional switching regulator using a PLL circuit has a coil L that is connected to an input voltage Vin, and a transistor 204 between the coil L and a ground. Furthermore, a transistor 205 is provided between an output terminal 209 and the contact point ds of the transistor 204 and coil L. The input voltage Vin, coil L, and transistors 204 and 205 configure a switching regulator circuit 210. An output terminal 209 is grounded through a smoothing condenser C.
The output voltage supplied to the output terminal 209 is input to a feedback circuit 208. The feedback circuit 208 increases the frequency of the control pulse signal that is output when a high output voltage is received, and decreases the frequency of the control pulse signal that is output when a low output voltage is received. A control pulse signal LMOS output from the feedback circuit 208 is supplied to the PLL circuit 201. Similar to a normal PLL circuit, the PLL circuit 201 includes a phase comparator, a filter for integrating the phase comparator output, and a voltage control oscillator (VCO) for generating a pulse at a frequency in accordance with the integrated voltage value.
The operation of the PLL circuit 201 is described below using FIG. 2A to 2C. The PLL circuit 201 shown in FIG. 2A is configured by a phase comparator 21, a filter 22, and a voltage control oscillator (VCO) 23. FIG. 2B shows an operation timing chart for the control pulse signal LMOS input to the phase comparator 21, signal driver-L, output in PLL of the phase comparator 21, and output pulse PLL of the PLL circuit 201.
When the control pulse signal LMOS and signal driver L are input to the phase comparator 21, the phase difference between the two signals is compared. The detected phase difference φ is fixed. The phase comparator 21 outputs an output in PLL based on the detected phase difference φ. FIG. 2C shows the response characteristics of the phase comparator 21. The phase comparator 21 outputs a potential that is proportional to the detected phase difference φ. The output in PLL from the phase comparator 21 passes through the filter 22, and is input to the voltage control oscillator (VCO) 23. The voltage control oscillator (VCO) 23 outputs an output pulse PLL at a frequency corresponding to the potential of the output in PLL.
Returning now to FIG. 1, the output pulse PLL from the PLL circuit 201 passes through a Schmitt trigger circuit ST1, and is input to a reset terminal R of a flip-flop circuit 202. The voltage at the connecting point ds is supplied to a set terminal S of the flip-flop circuit 202 through a Schmitt trigger circuit ST2. The output Q of the flip-flop circuit 202 is supplied to the gate terminal of a transistor 204 through a buffer circuit 203. Furthermore, the output Q of the flip-flop circuit 202 is fed back to the PLL circuit 201 through the buffer circuit 203. A pulse signal generated in a drive circuit 206 is supplied to the gate terminal of a transistor 205 through a buffer circuit 207.
The operation of the switching regulator of FIG. 1 is described below.
FIG. 3 is an operation timing chart of the switching regulator of FIG. 1. The operation timing chart shows the operation waveforms of the control pulse signal LMOS which is an output from the feedback circuit 208, the output pulse PLL from the PLL circuit 201, the signal driverL input to the gate terminal of the transistor 204, the voltage Vds at the connection point ds, the current IL flowing through the coil L, and the output signal driverH from the drive circuit 206. The PLL circuit 201 performs controls so as to synchronize the rise of the signal driverL with the rise of the control pulse signal LMOS.
The operation of the conventional switching regulator of the figure during the normal operation shown in FIG. 3 is described below.
First, the transistor 204 is turned ON when the signal driverL changes to H level with the timing at which the control pulse signal LMOS becomes H level (time t0). At this time, the coil L is connected between the input power source Vin and a ground. As a result, the current IL flowing through the coil L gradually increases, and energy accumulates in the coil L. The feedback circuit 208 controls the time t1 to turn OFF the transistor 204 since the period during which the transistor 204 is turned ON is controlled in accordance with the output voltage supplied to the output terminal 209. That is, the transistor 204 is turned OFF when the signal driverL is set to L level at time t1.
The signal driverH input to the gate terminal of the transistor 205 changes to H level at time t1, at which the signal driverL becomes L level, the transistor 204 is turned OFF, the voltage Vds rises, and the potential between both ends of the transistor 205 becomes zero (Vds=V209). While the signal driverH is H level, power is output to the output terminal 209, and the voltage Vds at the contact point ds remains fixed. Then, the signal driverH changes to L level at time t2, at which the current IL flowing through the coil L becomes zero. Thereafter, the current IL reverse flows, and the voltage Vds drops and becomes zero at time t3.
Anomalous operation of the conventional switching regulator is described below. Anomalous operation of the conventional switching regulator is generated by a change in the PLL output pulse caused by current noise or the like.
At time T0 shown in FIG. 3, a delay is generated in the PLL output pulse (D1), and the H level is maintained regardless of the timing at which the level must change to L level. Thus, there is also a delay generated in the timing of the fall of the signal driverL (D2). Because a delay is also generated in the fall of the signal driverL, the current increase in the current IL flowing through the coil L is not halted at time T0 at which the signal driverH attains H level. As a result, energy in excess of the energy during normal operation accumulates in the coil L (D3). Then, a condition obtains in which a positive current IL flows at time T1 at which the signal driverH reaches L level, although the current IL becomes zero at time T1 during normal operation. At time T2 at which the current IL actually becomes zero, the signal driverH has already become L level, and the energy accumulated in the coil L is lost without being discharged to the output terminal 209 side.
During anomalous operation of a conventional switching regulator, a process is performed to stop the drive circuit 206 to stop the H level output of the signal driverH at the stage in which one cycle has been completed after the anomalous operation has been generated. This stopping process determines that anomalous operation has occurred and performs a process D5 to stop the H level output of the signal driver H, when a rise in the signal driverL has not been detected within the range of a predetermined time D4 in preparation for the rise of the control pulse signal LMOS. This process temporarily stops output in order to reset the operation due to the unstable operation of the switching regulator.
The energy accumulated in the coil is not released to the output terminal when the transistor operation has been stopped for one cycle in order to correct the timing shift. The large power loss of the switching regulator at this time is extremely inefficient.